Hsu Yu-Hsuan, Lin Xin-Dai, Lin Yi-Hsin, Wuu Dong-Sing, Horng Ray-Hua
Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, 30010, Taiwan, ROC.
Department of Photonics, College of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, 30010, Taiwan, ROC.
Discov Nano. 2024 Aug 16;19(1):129. doi: 10.1186/s11671-024-04078-6.
In this study, arrays of μLEDs in four different sizes (5 × 5 μm, 10 × 10 μm, 25 × 25 μm, 50 × 50 μm) were fabricated using a flip-chip bonding process. Two passivation processes were investigated with one involving a single layer of SiO deposited using plasma-enhanced chemical vapor deposition (PECVD) and the other incorporating AlO deposited by atomic layer deposition (ALD) beneath the SiO layer. Owing to superior coverage and protection, the double-layers passivation process resulted in a three-order lower leakage current of μLEDs in the 5 μm chip-sized μLED arrays. Furthermore, higher light output power of μLEDs was observed in each chip-sized μLED array with double layers passivation. Particularly, the highest EQE value 21.9% of μLEDs array with 5 μm × 5 μm chip size was achieved with the double-layers passivation. The EQE value of μLEDs array was improved by 4.4 times by introducing the double-layers passivation as compared with that of μLEDs array with single layer passivation. Finally, more uniform light emission patterns were observed in the μLEDs with 5 μm × 5 μm chip size fabricated by double-layer passivation process using ImageJ software.
在本研究中,采用倒装芯片键合工艺制作了四种不同尺寸(5×5μm、10×10μm、25×25μm、50×50μm)的μLED阵列。研究了两种钝化工艺,一种是使用等离子体增强化学气相沉积(PECVD)沉积单层SiO,另一种是在SiO层下方采用原子层沉积(ALD)沉积AlO。由于具有优异的覆盖和保护性能,双层钝化工艺使5μm芯片尺寸的μLED阵列中的μLED泄漏电流降低了三个数量级。此外,在每个采用双层钝化的芯片尺寸μLED阵列中,观察到μLED的光输出功率更高。特别是,采用双层钝化实现了5μm×5μm芯片尺寸的μLED阵列的最高EQE值21.9%。与单层钝化的μLED阵列相比,引入双层钝化使μLED阵列的EQE值提高了4.4倍。最后,使用ImageJ软件观察到,通过双层钝化工艺制作的5μm×5μm芯片尺寸的μLED具有更均匀的发光图案。