Zhang Wenpeng, Wei Qun, Jia Xiaofei, He Liang
School of Physics, Xidian University, Xi'an 710071, China.
School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071, China.
Nanomaterials (Basel). 2024 Aug 18;14(16):1359. doi: 10.3390/nano14161359.
As field effect transistors are reduced to nanometer dimensions, experimental and theoretical research has shown a gradual change in noise generation mechanisms. There are few studies on noise theory for small nanoscale transistors, and Monte Carlo (MC) simulations mainly focus on 2D devices with larger nanoscale dimensions. In this study, we employed MC simulation techniques to establish a 3D device simulation process. By setting device parameters and writing simulation programs, we simulated the raw data of channel current noise for a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) with a 10 nm channel length and calculated the drain output current based on these data, thereby achieving static testing of the simulated device. Additionally, this study obtained a 3D potential distribution map of the device channel surface area. Based on the original data from the simulation analysis, this study further calculated the power spectral density of the channel current noise and analyzed how the channel current noise varies with gate voltage, source-drain voltage, temperature, and substrate doping density. The results indicate that under low-temperature conditions, the channel current noise of the 10 nm MOSFET is primarily composed of suppressed shot noise, with the proportion of thermal noise in the total noise slightly increasing as temperature rises. Under normal operating conditions, the channel current noise characteristics of the 10 nm MOSFET device are jointly characterized by suppressed shot noise, thermal noise, and cross-correlated noise. Among these noise components, shot noise is the main source of noise, and its suppression degree decreases as the bias voltage is reduced. These findings are consistent with experimental observations and theoretical analyses found in the existing literature.
随着场效应晶体管尺寸缩小至纳米级别，实验和理论研究表明噪声产生机制逐渐发生变化。针对小型纳米级晶体管的噪声理论研究较少，蒙特卡罗（MC）模拟主要集中在较大纳米尺寸的二维器件上。在本研究中，我们采用MC模拟技术建立了三维器件模拟流程。通过设置器件参数并编写模拟程序，我们模拟了沟道长度为10nm的硅基金属氧化物半导体场效应晶体管（MOSFET）的沟道电流噪声原始数据，并基于这些数据计算了漏极输出电流，从而实现了对模拟器件的静态测试。此外，本研究还获得了器件沟道表面积的三维电势分布图。基于模拟分析的原始数据，本研究进一步计算了沟道电流噪声的功率谱密度，并分析了沟道电流噪声如何随栅极电压、源漏电压、温度和衬底掺杂密度而变化。结果表明，在低温条件下，10nm MOSFET的沟道电流噪声主要由抑制型散粒噪声组成，随着温度升高，热噪声在总噪声中的占比略有增加。在正常工作条件下，10nm MOSFET器件的沟道电流噪声特性由抑制型散粒噪声、热噪声和互相关噪声共同表征。在这些噪声分量中，散粒噪声是主要噪声源，其抑制程度随着偏置电压降低而减小。这些发现与现有文献中的实验观察结果和理论分析一致。
