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未来的晶体管。

The future transistors.

机构信息

Department of Electrical and Computer Engineering, University of California Santa Barbara, Santa Barbara, CA, USA.

Advanced Logic and Memory Technology, IBM Research, Albany, NY, USA.

出版信息

Nature. 2023 Aug;620(7974):501-515. doi: 10.1038/s41586-023-06145-x. Epub 2023 Aug 16.

DOI:10.1038/s41586-023-06145-x
PMID:37587295
Abstract

The metal-oxide-semiconductor field-effect transistor (MOSFET), a core element of complementary metal-oxide-semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

摘要

金属-氧化物半导体场效应晶体管(MOSFET)是互补金属氧化物半导体(CMOS)技术的核心元件,是自工业革命以来最重大的发明之一。受集成电路产品对更高速度、更高能效和更高集成密度需求的驱动,在过去的六十年中,MOSFET 的物理栅极长度已缩小到 20 纳米以下。然而,在保持低功耗的情况下进一步缩小晶体管的尺寸,即使对于最先进的鳍式场效应晶体管(finFET)来说,也变得越来越具有挑战性。

在这里,我们全面评估了现有的和未来的 CMOS 技术,并根据为 FET 缩放建立的分层框架,讨论了基于亚 10 纳米栅长的 FET 设计所面临的挑战和机遇。我们的评估重点是基于从以前的缩放工作中获得的知识以及使晶体管与未来逻辑集成电路产品相关所需的研究工作,来确定最有前途的亚 10 纳米栅长 MOSFET。我们还详细阐述了对超越 MOSFET 的未来晶体管以及潜在创新机遇的展望。我们预计,晶体管技术的创新将继续在推动未来的材料、器件物理和拓扑结构、异质垂直和水平集成以及计算技术方面发挥核心作用。

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