Parasitic Capacitance in High-Density Neural Electrode Arrays: Sources and Evaluation Methods.

OBJECTIVE

This study aims to identify sources of parasitic capacitance in high-density neural electrode arrays and to provide an approach for evaluating their associated capacitance values. We also represent the effect of parasitic capacitance on the electrochemical properties of electrodes.

METHODS

Electrochemical impedance spectroscopy (EIS) and voltage transient (VT) measurements were employed to assess the parasitic capacitance of a 16-channel ultramicro-sized electrode array (UMEA) (8 × 25 µm electrode sites). The effect of parasitic capacitance on cyclic voltammetry (CV), EIS, and VT measurements of 20-µm diameter electrodes was assessed by comparing two different array designs: narrow and wide trace arrays.

RESULTS

The capacitive leakage currents and charge during CV measurements were not significant, however, during current pulsing 34% underestimation of the maximum charge injection capacity corresponded to capacitive leakage. Capacitive leakage during EIS resulted in an underestimation of the electrode impedance at frequencies >1.5 kHz.

CONCLUSION

The electrode design and insulation thickness can play a significant role in determining the amount of capacitive leakage during current pulsing and EIS at higher frequencies.

SIGNIFICANCE

Determining the sources and levels of capacitive leakage current in high-density neural electrode arrays, enables us to correct the measured value for the leakage current and thus estimate the electrode impedance and stimulation thresholds more accurately. This study highlights the importance of electrode design in developing high-density arrays with minimum capacitive leakage.