Han Yinhe, Xu Haobo, Lu Meixuan, Wang Haoran, Huang Junpei, Wang Ying, Wang Yujie, Min Feng, Liu Qi, Liu Ming, Sun Ninghui
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China.
University of Chinese Academy of Sciences, Beijing 100190, China.
Fundam Res. 2023 Dec 29;4(6):1431-1441. doi: 10.1016/j.fmre.2023.10.020. eCollection 2024 Nov.
As Moore's Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maximum reticle area, cost, and manufacturing yield, the chip's area cannot be continuously increased, and it encounters what is known as the "area-wall". In this paper, we provide a detailed analysis of the area-wall and propose a practical solution, the Big Chip, as a novel chip form to continuously improve performance. We introduce a performance model for evaluating Big Chip and discuss its architecture. Finally, we derive the future development trends of the Big Chip.
随着摩尔定律的终结，通过晶体管缩放来实现高性能芯片变得越来越具有挑战性。为了提高性能，增加芯片面积以集成更多晶体管已成为一种必不可少的方法。然而，由于诸如最大掩模版面积、成本和制造良率等限制，芯片面积无法持续增加，从而遇到了所谓的“面积墙”问题。在本文中，我们对面积墙进行了详细分析，并提出了一种切实可行的解决方案——大芯片，作为一种新颖的芯片形式来持续提升性能。我们引入了一个用于评估大芯片的性能模型，并讨论了其架构。最后，我们推导了大芯片未来的发展趋势。
