Yousuf Osama, Hoskins Brian D, Ramu Karthick, Fream Mitchell, Borders William A, Madhavan Advait, Daniels Matthew W, Dienstfrey Andrew, McClelland Jabez J, Lueker-Boden Martin, Adam Gina C
Department of Electrical and Computer Engineering, George Washington University, Washington, DC, USA.
National Institute of Standards and Technology, Gaithersburg, MD, USA.
Nat Commun. 2025 Feb 1;16(1):1250. doi: 10.1038/s41467-025-56319-6.
Artificial neural networks have advanced due to scaling dimensions, but conventional computing struggles with inefficiencies due to memory bottlenecks. In-memory computing architectures using memristor devices offer promise but face challenges due to hardware non-idealities. This work proposes layer ensemble averaging-a hardware-oriented fault tolerance scheme for improving inference performance of non-ideal memristive neural networks programmed with pre-trained solutions. Simulations on an image classification task and hardware experiments on a continual learning problem with a custom 20,000-device prototyping platform show significant performance gains, outperforming prior methods at similar redundancy levels and overheads. For the image classification task with 20% stuck-at faults, accuracy improves from 40% to 89.6% (within 5% of baseline), and for the continual learning problem, accuracy improves from 55% to 71% (within 1% of baseline). The proposed scheme is broadly applicable to accelerators based on a variety of different non-volatile device technologies.
人工神经网络因规模维度的扩展而取得了进展，但传统计算由于内存瓶颈导致效率低下。使用忆阻器器件的内存计算架构具有潜力，但由于硬件的非理想性而面临挑战。这项工作提出了层集成平均法——一种面向硬件的容错方案，用于提高用预训练解决方案编程的非理想忆阻神经网络的推理性能。在图像分类任务上的模拟以及在一个定制的20000器件原型平台上针对持续学习问题进行的硬件实验表明，性能有显著提升，在类似的冗余水平和开销下优于先前的方法。对于存在20%固定故障的图像分类任务，准确率从40%提高到89.6%（在基线的5%以内），对于持续学习问题，准确率从55%提高到71%（在基线的1%以内）。所提出的方案广泛适用于基于各种不同非易失性器件技术的加速器。
