Lim Jae Gwang, Lee Sang Min, Park Sung-Jae, Kwak Joon Young, Jeong Yeonjoo, Kim Jaewook, Lee Suyoun, Park Jongkil, Hwang Gyu Weon, Lee Kyeong-Seok, Park Seongsik, Ju Byeong-Kwon, Jang Hyun Jae, Park Jong Keuk, Kim Inho
Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, Republic of Korea.
School of Electrical Engineering, Korea University, Seoul, Republic of Korea.
Front Neurosci. 2025 Mar 5;19:1516971. doi: 10.3389/fnins.2025.1516971. eCollection 2025.
In view of the growing volume of data, there is a notable research focus on hardware that offers high computational performance with low power consumption. Notably, neuromorphic computing, particularly when utilizing CMOS-based hardware, has demonstrated promising research outcomes. Furthermore, there is an increasing emphasis on the utilization of emerging synapse devices, such as non-volatile memory (NVM), with the objective of achieving enhanced energy and area efficiency. In this context, we designed a hardware system that employs memristors, a type of emerging synapse, for a 1T1R synapse. The operational characteristics of a memristor are dependent upon its configuration with the transistor, specifically whether it is located at the source (MOS) or the drain (MOD) of the transistor. Despite its importance, the determination of the 1T1R configuration based on the operating voltage of the memristor remains insufficiently explored in existing studies. To enable seamless array expansion, it is crucial to ensure that the unit cells are properly designed to operate reliably from the initial stages. Therefore, this relationship was investigated in detail, and corresponding design rules were proposed. SPICE model based on fabricated memristors and transistors was utilized. Using this model, the optimal transistor selection was determined and subsequently validated through simulation. To demonstrate the learning capabilities of neuromorphic computing, an SNN inference accelerator was implemented. This implementation utilized a 1T1R array constructed based on the validated 1T1R model developed during the process. The accuracy was evaluated using a reduced MNIST dataset. The results verified that the neural network operations inspired by brain functionality were successfully implemented in hardware with high precision and no errors. Additionally, traditional ADC and DAC, commonly used in DNN research, were replaced with DPI and LIF neurons, resulting in a more compact design. The design was further stabilized by leveraging the low-pass filter effect of the DPI circuit, which effectively mitigated noise.
鉴于数据量的不断增长，对于能够提供高计算性能且低功耗的硬件的研究备受关注。值得注意的是，神经形态计算，尤其是在使用基于CMOS的硬件时，已展现出颇具前景的研究成果。此外，人们越来越重视利用诸如非易失性存储器（NVM）等新兴突触器件，以实现更高的能量和面积效率。在此背景下，我们设计了一种硬件系统，该系统采用忆阻器（一种新兴突触类型）构建1T1R突触。忆阻器的工作特性取决于其与晶体管的配置，具体而言，取决于它位于晶体管的源极（MOS）还是漏极（MOD）。尽管其重要性，但现有研究中基于忆阻器工作电压确定1T1R配置的探索仍不充分。为了实现无缝阵列扩展，确保单元细胞从初始阶段就经过合理设计以可靠运行至关重要。因此，我们详细研究了这种关系，并提出了相应的设计规则。利用基于制造的忆阻器和晶体管的SPICE模型。使用该模型确定了最佳晶体管选择，并随后通过仿真进行了验证。为了展示神经形态计算的学习能力，实现了一个SNN推理加速器。该实现利用了基于在此过程中开发并经过验证的1T1R模型构建的1T1R阵列。使用简化的MNIST数据集评估了准确性。结果验证了受大脑功能启发的神经网络操作在硬件中成功以高精度且无错误地实现。此外，将DNN研究中常用的传统ADC和DAC替换为DPI和LIF神经元，从而实现了更紧凑的设计。通过利用DPI电路的低通滤波效应进一步稳定了设计，有效减轻了噪声。
