Lim Jae Gwang, Park Sung-Jae, Lee Sang Min, Jeong Yeonjoo, Kim Jaewook, Lee Suyoun, Park Jongkil, Hwang Gyu Weon, Lee Kyeong-Seok, Park Seongsik, Jang Hyun Jae, Ju Byeong-Kwon, Park Jong Keuk, Kim Inho
Center for Semiconductor Technology, Korea Institute of Science and Technology, Seoul, 02792, South Korea.
School of Electrical Engineering, Korea University, Seoul, 02841, South Korea.
Sci Rep. 2024 Aug 2;14(1):17915. doi: 10.1038/s41598-024-68359-x.
Neuromorphic computing research is being actively pursued to address the challenges posed by the need for energy-efficient processing of big data. One of the promising approaches to tackle the challenges is the hardware implementation of spiking neural networks (SNNs) with bio-plausible learning rules. Numerous research works have been done to implement the SNN hardware with different synaptic plasticity rules to emulate human brain operations. While a standard spike-timing-dependent-plasticity (STDP) rule is emulated in many SNN hardware, the various STDP rules found in the biological brain have rarely been implemented in hardware. This study proposes a CMOS-memristor hybrid synapse circuit for the hardware implementation of a Ca ion-based plasticity model to emulate the various STDP curves. The memristor was adopted as a memory device in the CMOS synapse circuit because memristors have been identified as promising candidates for analog non-volatile memory devices in terms of energy efficiency and scalability. The circuit design was divided into four sub-blocks based on biological behavior, exploiting the non-volatile and analog state properties of memristors. The circuit was designed to vary weights using an H-bridge circuit structure and PWM modulation. The various STDP curves have been emulated in one CMOS-memristor hybrid circuit, and furthermore a simple neural network operation was demonstrated for associative learning such as Pavlovian conditioning. The proposed circuit is expected to facilitate large-scale operations for neuromorphic computing through its scale-up.
为应对大数据高效能处理需求所带来的挑战，神经形态计算研究正在积极开展。应对这些挑战的一种有前景的方法是采用具有生物似然学习规则的脉冲神经网络（SNN）进行硬件实现。为了模拟人类大脑的运作，已经开展了大量研究工作来实现具有不同突触可塑性规则的SNN硬件。虽然许多SNN硬件中都模拟了标准的基于脉冲时间依赖可塑性（STDP）规则，但生物大脑中发现的各种STDP规则在硬件中却很少被实现。本研究提出了一种用于基于钙离子可塑性模型硬件实现的CMOS - 忆阻器混合突触电路，以模拟各种STDP曲线。忆阻器被用作CMOS突触电路中的存储器件，因为就能量效率和可扩展性而言，忆阻器已被确定为模拟非易失性存储器件的有前途的候选者。基于生物行为，利用忆阻器的非易失性和模拟状态特性，将电路设计分为四个子模块。该电路设计为使用H桥电路结构和脉宽调制来改变权重。在一个CMOS - 忆阻器混合电路中模拟了各种STDP曲线，此外还展示了用于诸如经典条件反射等联想学习的简单神经网络操作。通过扩大规模，预计所提出的电路将有助于神经形态计算的大规模操作。
