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一种用于神经元离子通道动力学模拟的基于组件的FPGA设计框架。

A component-based FPGA design framework for neuronal ion channel dynamics simulations.

作者信息

Mak Terrence S T, Rachmuth Guy, Lam Kai-Pui, Poon Chi-Sang

机构信息

Department of Systems Engineering and Engineering Management, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong.

出版信息

IEEE Trans Neural Syst Rehabil Eng. 2006 Dec;14(4):410-8. doi: 10.1109/TNSRE.2006.886727.

Abstract

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field-programmable gate array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the alpha-amino-3-hydroxy-5-methyl-4-isoxazole propionic acid (AMPA) and N-methyl-D-aspartate (NMDA) synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution, as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired.

摘要

诸如动态钳制和可植入大脑的神经假体装置等神经元-机器接口需要对神经元离子通道动力学进行实时模拟。现场可编程门阵列(FPGA)已成为适用于此类特定应用计算的高速数字平台。我们提出了一种用于神经元离子通道动力学模拟的高效且灵活的基于组件的FPGA设计框架,该框架克服了最近提出的基于内存的方法的某些局限性。采用并行处理策略以最小化计算延迟,并使用一种硬件高效的因式分解方法来计算神经元离子通道模型中的指数和除法函数,以节省资源消耗。在α-氨基-3-羟基-5-甲基-4-异恶唑丙酸(AMPA)和N-甲基-D-天冬氨酸(NMDA)突触离子通道模型的相应实现中,从理论和实验上比较了各种FPGA设计方法的性能。我们的结果表明,基于组件的设计框架提供了一种内存更经济的解决方案,以及对于大位宽更高效的逻辑利用率,而基于内存的方法可能适用于需要更高吞吐率的对时间要求严格的应用。

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