Wang Runchun M, Thakur Chetan S, van Schaik André
The MARCS Institute, University of Western Sydney, Sydney, NSW, Australia.
Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore, India.
Front Neurosci. 2018 Apr 10;12:213. doi: 10.3389/fnins.2018.00213. eCollection 2018.
This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.
本文介绍了一种大规模并行且可扩展的神经形态皮层模拟器，旨在模拟大型且结构相连的脉冲神经网络，例如皮层各区域的复杂模型。这项工作的主要新颖之处在于将神经形态架构抽象为以微柱和超柱表示的集群，类似于在神经生物学中观察到的基本结构单元。若不采用这种方法，模拟大规模全连接网络需要极大的内存来存储点对点连接的查找表。相反，我们基于新皮层中的结构连通性使用了一种新颖的架构，使得所有所需参数和连接都能存储在片上内存中。通过对内存进行编程，皮层模拟器可轻松重新配置以模拟不同的神经网络，而无需改变硬件结构。一种分层通信方案允许单个神经元具有高达20万个神经元的扇出。作为概念验证，在一块Altera Stratix V FPGA上的实现能够实时模拟2000万到26亿个漏电整合发放（LIF）神经元。我们通过模拟一个简化的听觉皮层（包含1亿个神经元）对系统进行了验证。这个皮层模拟器实现了每个神经元1.62微瓦的低功耗。随着商用FPGA板的出现，我们的系统为大规模脉冲神经网络的设计、实时模拟和分析提供了一个易于使用且可扩展的工具。
