Chaudhry Anurag, Ramamurthi Vishwanath, Fong Erin, Islam M Saif
Integrated NanoDevices and Systems Research, Department of Electrical and Computer Engineering, University of California, Davis, Davis, California 95616, USA.
Nano Lett. 2007 Jun;7(6):1536-41. doi: 10.1021/nl070325e. Epub 2007 May 27.
Laterally oriented single-crystal silicon nanowires are epitaxially grown between highly doped vertically oriented silicon electrodes in the form of nanobridges. Resistance values extracted from the current-voltage measurements for a large number of nanobridges with varying lengths and diameters are used to propose a model which highlights the relative contribution of the contact resistance to the total resistance for nanowire-based devices. It is shown that the contact resistance depends on the effective conducting cross-section area and hence is influenced by the presence of a surface depletion layer. On the basis of our measured data and constructed model, we estimated the specific contact resistance to be in the range 3.74 x 10(-6) to 5.02 x 10(-6) Omega cm2 for our epitaxial interfacing method. This value is at least an order of magnitude lower than that of any known contact made to nanowires with an evaporated metal film, a common method for integrating semiconductor nanowires in devices and circuits.
横向取向的单晶硅纳米线以纳米桥的形式在高掺杂的垂直取向硅电极之间外延生长。从大量具有不同长度和直径的纳米桥的电流 - 电压测量中提取的电阻值被用于提出一个模型，该模型突出了接触电阻对基于纳米线的器件总电阻的相对贡献。结果表明，接触电阻取决于有效导电横截面积，因此受到表面耗尽层存在的影响。基于我们测量的数据和构建的模型，对于我们的外延界面方法，我们估计比接触电阻在3.74×10⁻⁶至5.02×10⁻⁶Ω·cm²范围内。该值至少比用蒸发金属膜与纳米线形成的任何已知接触低一个数量级，蒸发金属膜是在器件和电路中集成半导体纳米线的常用方法。
