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堆叠多层交叉阵列电路的四维地址拓扑结构。

Four-dimensional address topology for circuits with stacked multilayer crossbar arrays.

机构信息

Hewlett-Packard Laboratories, 1501 Page Mill Road, MS1123, Palo Alto, CA 94304, USA.

出版信息

Proc Natl Acad Sci U S A. 2009 Dec 1;106(48):20155-8. doi: 10.1073/pnas.0906949106. Epub 2009 Nov 16.

Abstract

We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.

摘要

我们提出了一个拓扑框架,为构建和使用多层交叉阵列提供了一种简单而强大的电子电路架构,允许在超越横向特征尺寸缩放限制的情况下,实现忆阻器交叉点器件的集成密度显著提高。这样的电路的真正显著特征是,将 CMOL(CMOS + 分子尺度器件)概念从类似区域的接口扩展到三维系统,即大特征尺寸互补金属氧化物半导体(CMOS)衬底可以通过单个垂直过孔为多个交叉层提供高密度互连。忆阻器器件的物理位置被映射到一个四维逻辑地址空间,使得从 CMOS 衬底到堆叠交叉阵列中的每个器件都可以进行唯一的访问。这种混合架构与数字存储器、现场可编程门阵列和受生物启发的自适应网络兼容,并且与最先进的集成电路代工厂兼容。

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