Harvard Medical School, Boston, Massachusetts, United States of America.
PLoS One. 2012;7(9):e42492. doi: 10.1371/journal.pone.0042492. Epub 2012 Sep 12.
The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain- machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain- machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than [Formula: see text]. We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.
将神经活动解码为假肢设备的有意义的控制信号的能力对于开发临床有用的脑机接口（BMI）至关重要。此类系统需要从数十到数百个脑植入式记录电极获取输入，以提供稳健而准确的性能；为了实现这一主要功能，它们还应最大限度地降低功耗，以避免损坏神经组织；并且它们应该通过无线传输数据，以最大程度地降低与慢性经皮植入物相关的感染风险。因此，脑机接口的电子架构必须最小化尺寸和功耗，同时最大限度地提高在有限带宽无线信道上传输数据的能力。在这里，我们提出了一种具有极低计算复杂度的系统，专为实时解码神经信号而设计，适合高度可扩展的植入式系统。我们的可编程架构是一种通用计算机器的显式实现，模拟了积分和点火神经元网络的动态；它除了计数之外不需要任何算术运算，并且仅使用计算成本低廉的逻辑运算对神经信号进行解码。这种架构的简单性不会影响其通过大于[公式：见正文]的因子来压缩原始神经数据的能力。我们描述了一组基于这种计算架构的解码算法，其中一个算法旨在在植入系统内运行，最大限度地降低其功耗和数据传输带宽；以及一组用于学习、编程解码器和对解码输出进行后处理的互补算法，旨在在外部非植入单元中运行。估计植入部分的实现每秒需要不到 5000 次操作。因此，该部分的 32 通道现场可编程门阵列（FPGA）实现是节能的。我们通过解码行为啮齿动物的电生理数据来验证我们整个系统的性能。
