Qin Xi, Zhu Ming-Dong, Zhang Wen-Zhe, Lin Yi-Heng, Rui Ying, Rong Xing, Du Jiangfeng
Hefei National Laboratory for Physical Sciences at the Microscale and Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China.
Rev Sci Instrum. 2020 Feb 1;91(2):024708. doi: 10.1063/1.5141391.
A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.
本文报道了一种基于现场可编程门阵列（FPGA）的时间数字转换器（TDC），它在单个时间测量通道中结合了不同类型的延迟链。开发了一种新的TDC架构，并采用了FPGA芯片内部集成的进位链和DSP48E1加法器来实现高分辨率时间标记。单通道TDC的平均量化间隔大小为3.3 ps，单次测量精度为5.4 ps，最大采样率为250 MSa/s。单个TDC通道的微分非线性为-3.3 ps/+24.1 ps，积分非线性在-10.4 ps/+68.6 ps范围内。通过使用四个TDC通道测量一个输入信号，可以提高TDC性能，单次测量精度可达3.4 ps。由于采用了精密的TDC结构，只需少量数字资源就能实现皮秒级的时间测量分辨率。因此，所报道的TDC架构适用于需要对多个输入信号进行高时间分辨率测量的多通道应用。
