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基于二维极性可控晶体管的无掺杂互补逻辑门

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors.

作者信息

Resta Giovanni V, Balaji Yashwanth, Lin Dennis, Radu Iuliana P, Catthoor Francky, Gaillardon Pierre-Emmanuel, De Micheli Giovanni

机构信息

Integrated System Laboratory (LSI), School of Engineering , École Polytechnique Fédérale de Lausanne (EPFL) , CH-1015 Lausanne , Switzerland.

IMEC , Kapeldreef 75 , B-3001 Leuven , Belgium.

出版信息

ACS Nano. 2018 Jul 24;12(7):7039-7047. doi: 10.1021/acsnano.8b02739. Epub 2018 Jun 29.

Abstract

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the possibility of ambipolar conduction, tungsten diselenide (WSe) provides a platform for the efficient implementation of polarity-controllable transistors. These transistors use an additional gate, named polarity gate, that, due to the electrostatic doping of the Schottky junctions, provides a device-level dynamic control of their polarity, that is, n- or p-type. Here, we experimentally demonstrate a complete doping-free standard cell library realized on WSe without the use of either chemical or physical doping. We show a functionally complete family of complementary logic gates (INV, NAND, NOR, 2-input XOR, 3-input XOR, and MAJ) and, due to the reconfigurable capabilities of the single devices, achieve the realization of highly expressive logic gates, such as exclusive-OR (XOR) and majority (MAJ), with fewer transistors than possible in conventional complementary metal-oxide-semiconductor logic. Our work shows a path to enable doping-free low-power electronics on 2D semiconductors, going beyond the concept of unipolar physically doped devices, while suggesting a road to achieve higher computational densities in two-dimensional electronics.

摘要

属于过渡金属二硫属化物的原子级薄二维(2D)材料,因其物理和电学特性,是探索下一代半导体器件的理想载体。其中,由于双极传导的可能性,二硒化钨(WSe)为高效实现极性可控晶体管提供了一个平台。这些晶体管使用一个额外的栅极,称为极性栅极,由于肖特基结的静电掺杂,可对其极性(即n型或p型)进行器件级动态控制。在此,我们通过实验证明了在WSe上实现的一个完整的无掺杂标准单元库,且未使用化学或物理掺杂。我们展示了一个功能完整的互补逻辑门系列(反相器、与非门、或非门、2输入异或门、3输入异或门和多数门),并且由于单个器件的可重构能力,实现了高表达性逻辑门,如异或(XOR)和多数(MAJ),其晶体管数量比传统互补金属氧化物半导体逻辑中可能的数量更少。我们的工作展示了一条在二维半导体上实现无掺杂低功耗电子学的途径,超越了单极物理掺杂器件的概念,同时为在二维电子学中实现更高的计算密度指明了道路。

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