Orji N G, Badaroglu M, Barnes B M, Beitia C, Bunday B D, Celano U, Kline R J, Neisser M, Obeng Y, Vladar A E
National Institute of Standards and Technology, Gaithersburg, Maryland, 20899, USA.
Huawei Technologies, Leuven, Belgium.
Nat Electron. 2018;1. doi: 10.1038/s41928-018-0150-9.
The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.
半导体行业持续生产尺寸越来越小、形状越来越复杂且包含越来越多材料类型的器件。这些新器件的最终尺寸和功能将受到诸如散热、载流子迁移率和容错阈值等基本和工程限制的影响。目前,尚不清楚评估此类器件纳米级特征所需的最佳测量方法是什么,以及基本限制将如何影响所需的计量学。在此,我们回顾了用于集成电路的最先进尺寸计量方法,考虑了各种方法的优点、局限性和潜在改进。我们描述了集成电路器件设计和行业需求将如何影响光刻选项,进而影响计量学要求。我们还讨论了可能强大的新兴技术,并突出了目前尚无明显解决方案的测量问题。