Popov Vladimir P, Tikhonenko Fedor V, Antonov Valentin A, Tyschenko Ida E, Miakonkikh Andrey V, Simakin Sergey G, Rudenko Konstantin V
Rzhanov Institute of Semiconductor Physics SB RAS, 630090 Novosibirsk, Russia.
Valiev Institute of Physics and Technology RAS, 117218 Moscow, Russia.
Nanomaterials (Basel). 2021 Jan 22;11(2):291. doi: 10.3390/nano11020291.
Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The "diode-like" currents through the symmetric atomic layer deposited (ALD) HfO/AlO/HfO… nanolayers with a highest rectification coefficient 10 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides. The lowest leakages are observed through the stacks, with total AlO thickness values of 8-10 nm, which also provide a diffusive barrier for hydrogen. The dominant mechanism of electron transport through the built-in insulator at the weak field E < 1 MV/cm is thermionic emission. The Poole-Frenkel (PF) mechanism of emission from traps dominates at larger E values. The charge carriers mobility 100-120 cm/(V s) and interface states (IFS) density 1.2 × 10 cm are obtained for the n-p SIS structures with insulator HfO:AlO (10:1) after rapid thermal annealing (RTA) at 800 °C. The drain current hysteresis of pseudo-metal-oxide-semiconductor field effect transistor (MOSFET) with the memory window 1.2-1.3 V at the gate voltage |V| < ±2.5 V is maintained in the RTA treatment at T = 800-900 °C for these transistors.
具有高介电常数电介质的硅半导体-绝缘体-半导体（SIS）结构是用于光子和CMOS集成的一种很有前景的新型材料。通过对称原子层沉积（ALD）的HfO/AlO/HfO…纳米层观察到了“类二极管”电流，其最高整流系数为10，并通过键合和ALD工艺形成的上下异质界面的不对称性进行了解释。结果，在绝缘体两侧形成了不同的空间电荷区（SCR）。通过总AlO厚度值为8 - 10 nm的堆叠结构观察到最低泄漏电流，这也为氢提供了扩散阻挡层。在弱场E < 1 MV/cm时，电子通过内置绝缘体传输的主要机制是热电子发射。在较大E值时，陷阱发射的普尔-弗伦克尔（PF）机制占主导。对于在800°C进行快速热退火（RTA）后的具有绝缘体HfO:AlO（10:1）的n-p SIS结构，获得了载流子迁移率100 - 120 cm²/(V·s)和界面态（IFS）密度1.2×10¹² cm⁻²。对于这些晶体管，在800 - 900°C的RTA处理中，在栅极电压|V| < ±2.5 V时，具有1.2 - 1.3 V记忆窗口的伪金属氧化物半导体场效应晶体管（MOSFET）的漏极电流滞后得以保持。
