Liu Maomao, Jaiswal Hemendra Nath, Shahi Simran, Wei Sichen, Fu Yu, Chang Chaoran, Chakravarty Anindita, Liu Xiaochi, Yang Cheng, Liu Yanpeng, Lee Young Hee, Perebeinos Vasili, Yao Fei, Li Huamin
Department of Electrical Engineering, University at Buffalo, The State University of New York, Buffalo, New York 14260, United States.
Department of Materials Design and Innovation, University at Buffalo, The State University of New York, Buffalo, New York 14260, United States.
ACS Nano. 2021 Mar 23;15(3):5762-5772. doi: 10.1021/acsnano.1c01503. Epub 2021 Mar 11.
Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the "Boltzmann tyranny" that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic refrigeration effect with an effective electron temperature of ∼145 K in the monolayer MoS, which enables the transport factor lowering and thus the steep-slope switching (across for three decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS FET. Especially, a record-high sub-60-mV/decade current density (over 1 μA/μm) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the potential of a 2D Dirac-source cold electron transistor as a steep-slope transistor concept for future energy-efficient nanoelectronics.
在传统的三维(3D)或二维(2D)半导体中,室温下的费米 - 狄拉克电子热激发会产生能量分布具有相对较长热尾的热电子。这些热电子构成了一个被称为“玻尔兹曼暴政”的基本障碍,它限制了亚阈值摆幅(SS),从而限制了3D和2D场效应晶体管(FET)的最小功耗。在此,我们研究了一种基于石墨烯(Gr)的冷电子注入,其中Gr充当狄拉克源,在室温下为冷电子提供局部电子密度分布和短热尾。这些冷电子对应于单层MoS₂中有效电子温度约为145 K的电子制冷效应,这使得单层MoS₂ FET的传输因子降低,从而实现陡坡开关(在室温下跨越三个数量级,最小SS为29 mV/decade)。特别是,与使用2D或3D沟道材料的传统陡坡技术(如隧道FET或负电容FET)相比,可以实现创纪录的低于60 mV/decade的电流密度(超过1 μA/μm)。我们的工作展示了二维狄拉克源冷电子晶体管作为未来节能纳米电子学陡坡晶体管概念的潜力。