Dragas Jelena, Jäckel David, Franke Felix, Hierlemann Andreas
ETH Zurich, Department of Biosystems Science and Engineering, Basel, Switzerland.
IEEE Int Symp Circuits Syst Proc. 2014;2014:658-661. doi: 10.1109/ISCAS.2014.6865221. Epub 2014 Jul 28.
Spike overlaps occur frequently in dense neuronal network recordings, creating difficulties for spike sorting. Brainmachine interfaces and studies of neuronal network dynamics often require that an accurate spike sorting be done in real time, with low execution latency (on the order of milliseconds). Moreover, modern neuronal recording systems that feature thousands of electrodes require processing of several tens or hundreds of neurons in parallel. The existing algorithms capable of performing spike overlap decomposition are generally very complex and unsuitable for real-time implementation, especially for an on-chip implementation. Here we present a hardware device capable of processing pair-wise spike overlaps in real time. A previously-published spike sorting algorithm, which is not suitable for processing data of large neuronal networks with low latency, has been optimized for high-throughput, low-latency hardware implementation. The designed hardware architecture has been verified on an FPGA platform. Low spike sorting error rates (0.05) for overlapping spikes have been achieved with a latency of 2.75 ms, rendering the system particularly suitable for use in closed-loop experiments.
在密集的神经元网络记录中，尖峰重叠频繁出现，给尖峰分类带来了困难。脑机接口和神经元网络动力学研究通常要求实时进行精确的尖峰分类，且执行延迟较低（在毫秒量级）。此外，具有数千个电极的现代神经元记录系统需要并行处理数十个或数百个神经元。现有的能够执行尖峰重叠分解的算法通常非常复杂，不适合实时实现，尤其是片上实现。在此，我们展示了一种能够实时处理成对尖峰重叠的硬件设备。一种先前发表的尖峰分类算法，虽然不适合以低延迟处理大型神经元网络的数据，但已针对高通量、低延迟的硬件实现进行了优化。所设计的硬件架构已在FPGA平台上得到验证。对于重叠尖峰，实现了低至0.05的尖峰分类错误率，延迟为2.75毫秒，使得该系统特别适用于闭环实验。
