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一种基于RRAM交叉阵列的神经形态脑接口,用于高通量实时尖峰分类。

A Neuromorphic Brain Interface based on RRAM Crossbar Arrays for High Throughput Real-time Spike Sorting.

作者信息

Shi Yuhan, Ananthakrishnan Akshay, Oh Sangheon, Liu Xin, Hota Gopabandhu, Cauwenberghs Gert, Kuzum Duygu

机构信息

Electrical and Computer Engineering Department. G. Cauwenberghs is with Bioengineering Department, University of California at San Diego, San Diego, CA 92093, USA.

出版信息

IEEE Trans Electron Devices. 2022 Apr;69(4):2137-2144. doi: 10.1109/ted.2021.3131116. Epub 2021 Dec 13.

Abstract

Real-time spike sorting and processing are crucial for closed-loop brain-machine interfaces and neural prosthetics. Recent developments in high-density multi-electrode arrays with hundreds of electrodes have enabled simultaneous recordings of spikes from a large number of neurons. However, the high channel count imposes stringent demands on real-time spike sorting hardware regarding data transmission bandwidth and computation complexity. Thus, it is necessary to develop a specialized real-time hardware that can sort neural spikes on the fly with high throughputs while consuming minimal power. Here, we present a real-time, low latency spike sorting processor that utilizes high-density CuO resistive crossbars to implement in-memory spike sorting in a massively parallel manner. We developed a fabrication process which is compatible with CMOS BEOL integration. We extensively characterized switching characteristics and statistical variations of the CuO memory devices. In order to implement spike sorting with crossbar arrays, we developed a template matching-based spike sorting algorithm that can be directly mapped onto RRAM crossbars. By using synthetic and recordings of extracellular spikes, we experimentally demonstrated energy efficient spike sorting with high accuracy. Our neuromorphic interface offers substantial improvements in area (1000× less area), power (200× less power), and latency (4.8s latency for sorting 100 channels) for real-time spike sorting compared to other hardware implementations based on FPGAs and microcontrollers.

摘要

实时尖峰排序和处理对于闭环脑机接口和神经假体至关重要。近年来,具有数百个电极的高密度多电极阵列的发展使得能够同时记录大量神经元的尖峰。然而,高通道数对实时尖峰排序硬件在数据传输带宽和计算复杂度方面提出了严格要求。因此,有必要开发一种专门的实时硬件,能够以高吞吐量实时对神经尖峰进行排序,同时功耗最小。在此,我们展示了一种实时、低延迟的尖峰排序处理器,它利用高密度CuO电阻交叉阵列以大规模并行方式实现内存中的尖峰排序。我们开发了一种与CMOS后端集成兼容的制造工艺。我们广泛表征了CuO存储器件的开关特性和统计变化。为了用交叉阵列实现尖峰排序,我们开发了一种基于模板匹配的尖峰排序算法,该算法可以直接映射到RRAM交叉阵列上。通过使用合成数据和细胞外尖峰记录,我们通过实验证明了具有高精度的节能尖峰排序。与基于FPGA和微控制器的其他硬件实现相比,我们的神经形态接口在面积(面积减少约1000倍)、功耗(功耗减少约200倍)和延迟(对100个通道进行排序的延迟为4.8秒)方面为实时尖峰排序提供了显著改进。

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