Chen Yi-Yueh, Lee Feng-Ming, Lin Yu-Yu, Lee Chih-Hsiung, Chen Wei-Chen, Shu Che-Kai, Lin Su-Jien, Chang Shou-Yi, Lu Chih-Yuan
Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan.
Quality Engineering Center, Macronix International Co., Ltd., Hsinchu 30078, Taiwan.
Materials (Basel). 2022 May 19;15(10):3640. doi: 10.3390/ma15103640.
To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.
为了降低浮栅器件的电荷泄漏，并朝着更小的结构尺寸和更高的元件性能提升存储器件的操作性能，本研究开发了两种由pn型多晶硅或np型多晶硅组成的新型浮栅。研究了它们的微观结构和元素组成，并测量了薄层电阻、阈值电压和擦除电压。实验结果和电荷模拟表明，通过在浮栅中形成n-p结，薄层电阻增加，并且由于在结界面处形成作为本征势垒的载流子耗尽区，电荷泄漏减少。此外，np型浮栅的阈值电压和擦除电压升高，这表明在不应用新材料或改变物理结构的情况下，可以有效地提高浮栅在存储器件操作中的性能。
