一款在20纳米Cyclone-10 GX现场可编程门阵列中实现的4.8皮秒均方根分辨率时间数字转换器。

A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX field-programmable gate array.

作者信息

Yu Xin, Xia Haojie, Li Weishi, Zhang Jin, Chang Songtao

机构信息

Anhui Province Key Laboratory of Measuring Theory and Precision Instrument, School of Instrument Science and Optoelectronics Engineering, Hefei University of Technology, Hefei 230009, Anhui, China.

出版信息

Rev Sci Instrum. 2022 Aug 1;93(8):085001. doi: 10.1063/5.0090783.

DOI:10.1063/5.0090783

PMID:36050100

Abstract

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20 nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8 ps root-mean-square resolution and a 5.68 ps least-significant-bit resolution.

摘要

在时间间隔测量中，提高基于现场可编程门阵列（FPGA）的时间数字转换器（TDC）的分辨率和精度是很困难的。在本研究中，我们设计了一种先行进位延迟链结构，并将交错采样方法与在线校准和bin重新调整方法相结合来实现一个TDC。我们利用了应用于Cyclone-10 GX（10CX220YF780E5G）的自适应逻辑模块单元，这是一款20纳米低功耗、低成本的FPGA。在这款新一代FPGA中，我们实现了高精度的时间间隔测量，其均方根分辨率为4.8皮秒，最低有效位分辨率为5.68皮秒，超过了我们之前所有的工作。