Tao Xinge, Liu Lu, Xu Jingping
School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074, China.
Nanomaterials (Basel). 2022 Dec 7;12(24):4352. doi: 10.3390/nano12244352.
An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS NCFET is fabricated using a single HfZrAlO (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the HfZrO (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 10. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/AlO stack gates.
降低集成电路功耗的一种有效方法是在栅极堆叠中引入负电容（NC）。通常，负电容场效应晶体管（NCFET）使用负电容层和正电容层作为堆叠栅极，这不利于器件的缩小。在本研究中，使用单一的铪锆铝氧化物（HZAO）层作为栅极电介质制造了一种具有陡峭斜率且无滞后现象的二硫化钼NCFET。通过将几个铝原子掺入铪锆氧化物（HZO）薄膜中，可以在HZAO薄膜中同时实现负电容和正电容，并实现良好的电容匹配。这使得相关NCFET具有出色的电学性能，包括在几乎四个数量级的漏极电流范围内具有22.3 mV/dec的低亚阈值摆幅、几乎无滞后现象以及9.4×10的高开/关电流比。因此，与传统的HZO/AlO堆叠栅极相比，使用单一的HZAO层作为栅极电介质在制造高性能、低功耗NCFET方面具有巨大潜力。
