Zhang Wenxuan, Xu Xing, Cheng Zhengxi
Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China.
Sensors (Basel). 2024 Mar 13;24(6):1841. doi: 10.3390/s24061841.
We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3-B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.
我们分析了影响CMOS图像传感器线性输出范围的几个因素，包括电荷转移时间、复位晶体管电源电压、积分电容的电容、 pinned光电二极管（PPD）的n阱掺杂以及输出缓冲器。测试芯片采用0.18μm CMOS图像传感器（CIS）工艺制造，包含六个通道。通道B1和B2为10μm像素，通道B3 - B6为20μm像素，相应的像素阵列分别为1×2560和1×1280。浮动扩散（FD）电容在10 fF至23.3 fF之间变化，并且在PPD的n阱掺杂中采用了两种不同的设计。实验结果表明，优化FD电容和PPD设计可分别将线性输出范围提高37%和32%。对于较大的像素尺寸，延长传输门（TG）采样时间可使线性输出范围增加超过60%。此外，优化输出缓冲器的设计可以缓解对线性输出范围的限制。用于降噪的较低复位电压对线性输出范围没有显著影响。此外，这些方法可以在不显著放大读出噪声的情况下提高线性输出范围。这些发现表明，像素的线性输出范围不仅受像素设计的影响，还受操作条件的影响。最后，我们详细分析了PPD n阱掺杂浓度和TG采样时间对线性输出范围的影响。这为设计人员提供了对像素中如何引入非线性的清晰理解，为高线性像素的设计提供了有价值的见解。
