Jang MoonHyung, Hays Maddy, Yu Wei-Han, Lee Changuk, Caragiulo Pietro, Ramkaj Athanasios, Wang Pingyu, Phillips A J, Vitale Nick, Tandon Pulkit, Yan Pumiao, Mak Pui-In, Chae Youngcheol, Chichilnisky E J, Murmann Boris, Muratore Dante G
Department of Electrical Engineering, Stanford University, CA 94305 USA.
Department of Bioengineering, Stanford University, CA 94305 USA.
IEEE J Solid-State Circuits. 2024 Apr;59(4):1123-1136. doi: 10.1109/jssc.2023.3344798. Epub 2023 Dec 29.
This paper presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain-computer interfaces. The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse position modulation-based active digital pixels with a global single-slope analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 m that can be directly matched to a high-density microelectrode array. The pixel achieves 7.4 V input-referred noise with a -3 dB bandwidth of 300-Hz to 5-kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 m) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.
本文提出了一种用于单细胞分辨率高带宽脑机接口的数据压缩神经记录集成电路。该集成电路的特点是在数字化过程中采用线或有损压缩，从而防止数据泛滥和大量数据移动。通过丢弃神经信号不需要的基线样本，输出数据速率平均降低了146倍，同时允许重建尖峰样本。记录阵列由基于脉冲位置调制的有源数字像素和全局单斜率模数转换方案组成，这使得像素设计具有低功耗和紧凑性，布线显著简单，阵列读出能量低。该神经记录集成电路采用28纳米CMOS工艺制造，具有1024个通道（即32×32阵列），像素间距为36微米，可以直接与高密度微电极阵列匹配。该像素在300赫兹至5千赫兹的-3分贝带宽下实现了7.4伏输入参考噪声，同时从单一1伏电源仅消耗268纳瓦功率。在迄今为止发表的最先进的神经记录集成电路中，该集成电路实现了每通道最小面积（36×36微米）和最高能量效率。
