IBM Research - Zürich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland.
Nano Lett. 2011 Oct 12;11(10):4195-9. doi: 10.1021/nl202103a. Epub 2011 Aug 31.
We report on the electrical characterization of one-sided p(+)-si/n-InAs nanowire heterojunction tunnel diodes to provide insight into the tunnel process occurring in this highly lattice mismatched material system. The lattice mismatch gives rise to dislocations at the interface as confirmed by electron microscopy. Despite this, a negative differential resistance with peak-to-valley current ratios of up to 2.4 at room temperature and with large current densities is observed, attesting to the very abrupt and high-quality interface. The presence of dislocations and other defects that increase the excess current is evident in the first and second derivative of the I-V characteristics as distinct peaks arising from trap-and phonon-assisted tunneling via the corresponding defect levels. We observe this assisted tunneling mainly in the forward direction and at low reverse bias but not at higher reverse biases because the band-to-band generation rates are peaked in the InAs, which is also confirmed by modeling. This indicates that most of the peaks are due to dislocations and defects in the immediate vicinity of the interface. Finally, we also demonstrate that these devices are very sensitive to electrical stress, in particular at room temperature, because of the extremely high electrical fields obtained at the abrupt junction even at low bias. The electrical stress induces additional defect levels in the band gap, which reduce the peak-to-valley current ratios.
我们报告了单边 p(+)-si/n-InAs 纳米线异质结隧道二极管的电学特性，以深入了解在这种高度晶格失配的材料系统中发生的隧道过程。正如电子显微镜所证实的那样，晶格失配导致了界面处的位错。尽管如此，在室温下仍观察到具有高达 2.4 的峰谷电流比的负微分电阻，并且具有大电流密度，这证明了界面非常陡峭和高质量。在 I-V 特性的一阶和二阶导数中，可以明显看出存在增加过剩电流的位错和其他缺陷，这是由于通过相应的缺陷能级进行的陷阱和声子辅助隧道。我们观察到这种辅助隧道主要发生在正向方向和低反向偏压下，但在较高的反向偏压下不会发生，因为带隙中的带对带产生率在 InAs 中达到峰值，这也通过建模得到了证实。这表明，大多数峰都归因于界面附近的位错和缺陷。最后，我们还证明，由于在低偏压下甚至在低偏压下在陡峭结处获得的极高电场，这些器件对电应力非常敏感，特别是在室温下。电应力会在带隙中引入额外的缺陷能级，从而降低峰谷电流比。
