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基于晶圆级二维二硒化铪的忆阻器交叉阵列用于高能效神经网络硬件。

Wafer-Scale 2D Hafnium Diselenide Based Memristor Crossbar Array for Energy-Efficient Neural Network Hardware.

机构信息

Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore, 117583, Singapore.

Institute of Materials Research and Engineering, Agency for Science, Technology and Research, 2 Fusionopolis Way, Singapore, 138634, Singapore.

出版信息

Adv Mater. 2022 Jun;34(25):e2103376. doi: 10.1002/adma.202103376. Epub 2021 Sep 12.

Abstract

Memristor crossbar with programmable conductance could overcome the energy consumption and speed limitations of neural networks when executing core computing tasks in image processing. However, the implementation of crossbar array (CBA) based on ultrathin 2D materials is hindered by challenges associated with large-scale material synthesis and device integration. Here, a memristor CBA is demonstrated using wafer-scale (2-inch) polycrystalline hafnium diselenide (HfSe ) grown by molecular beam epitaxy, and a metal-assisted van der Waals transfer technique. The memristor exhibits small switching voltage (0.6 V), low switching energy (0.82 pJ), and simultaneously achieves emulation of synaptic weight plasticity. Furthermore, the CBA enables artificial neural network with a high recognition accuracy of 93.34%. Hardware multiply-and-accumulate (MAC) operation with a narrow error distribution of 0.29% is also demonstrated, and a high power efficiency of greater than 8-trillion operations per second per Watt is achieved. Based on the MAC results, hardware convolution image processing can be performed using programmable kernels (i.e., soft, horizontal, and vertical edge enhancement), which constitutes a vital function for neural network hardware.

摘要

基于可编程电导的忆阻器交叉阵列有望克服神经网络在执行图像处理核心计算任务时的能耗和速度限制。然而,基于超薄二维材料的交叉阵列(CBA)的实现受到与大规模材料合成和器件集成相关的挑战的阻碍。在这里,使用通过分子束外延生长的晶圆级(2 英寸)多晶二硒化铪(HfSe )和金属辅助范德华转移技术展示了忆阻器 CBA。忆阻器表现出较小的开关电压(0.6 V)、低开关能量(0.82 pJ),并同时实现了突触权重可塑性的仿真。此外,CBA 实现了具有 93.34%高识别准确率的人工神经网络。还展示了具有 0.29%窄误差分布的硬件乘法累加(MAC)运算,以及超过 8 万亿次/秒每瓦的高功率效率。基于 MAC 结果,可以使用可编程核(即软、水平和垂直边缘增强)进行硬件卷积图像处理,这是神经网络硬件的重要功能。

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