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用于卷积神经网络中内存计算硬件的二维忆阻器阵列与硅选择器的异构集成。

Heterogeneous integration of 2D memristor arrays and silicon selectors for compute-in-memory hardware in convolutional neural networks.

作者信息

Jain Samarth, Li Sifan, Zheng Haofei, Li Lingqi, Fong Xuanyao, Ang Kah-Wee

机构信息

Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore, 117583, Singapore.

出版信息

Nat Commun. 2025 Mar 19;16(1):2719. doi: 10.1038/s41467-025-58039-3.

DOI:10.1038/s41467-025-58039-3
PMID:40108150
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC11923061/
Abstract

Memristor crossbar arrays (CBAs) based on two-dimensional (2D) materials have emerged as a potential solution to overcome the limitations of energy consumption and latency associated with conventional von Neumann architectures. However, current 2D memristor CBAs encounter specific challenges such as limited array size, high sneak path current, and lack of integration with peripheral circuits for hardware compute-in-memory (CIM) systems. In this work, we demonstrate a hardware CIM system leveraging heterogeneous integration of scalable 2D hafnium diselenide (HfSe) memristors and silicon (Si) selectors, as well as their integration with peripheral control-sensing circuits. The 32 × 32 one-selector-one-memristor (1S1R) array mitigates sneak current, achieving 89% yield. The integrated CBA demonstrates an improvement of energy efficiency and response time comparable to state-of-the-art 2D materials-based memristors. To take advantage of low latency devices for achieving low energy systems, we use time-domain sensing circuits with the CBA, whose power consumption surpasses that of analog-to-digital converters (ADCs) by 2.5 folds. The implemented full-hardware binary convolutional neural network (CNN) achieves remarkable accuracy (97.5%) in a pattern recognition task. Additionally, in-built activation functions enhance the energy efficiency of the system. This silicon-compatible heterogeneous integration approach presents a promising hardware solution for artificial intelligence (AI) applications.

摘要

基于二维(2D)材料的忆阻器交叉阵列(CBA)已成为克服与传统冯·诺依曼架构相关的能耗和延迟限制的潜在解决方案。然而,当前的二维忆阻器CBA面临着特定的挑战,如阵列尺寸有限、高潜行路径电流,以及缺乏与硬件内存计算(CIM)系统的外围电路集成。在这项工作中,我们展示了一种硬件CIM系统,该系统利用了可扩展的二维二硒化铪(HfSe)忆阻器和硅(Si)选择器的异质集成,以及它们与外围控制传感电路的集成。32×32的单选择器单忆阻器(1S1R)阵列减轻了潜行电流,良品率达到89%。集成的CBA在能量效率和响应时间方面的表现与基于二维材料的最先进忆阻器相当。为了利用低延迟设备实现低能耗系统,我们将时域传感电路与CBA一起使用,其功耗比模数转换器(ADC)高出2.5倍。所实现的全硬件二进制卷积神经网络(CNN)在模式识别任务中取得了显著的准确率(97.5%)。此外,内置的激活函数提高了系统的能量效率。这种与硅兼容的异质集成方法为人工智能(AI)应用提供了一种很有前景的硬件解决方案。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/beaaee90db5d/41467_2025_58039_Fig6_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/4f2356ca93f5/41467_2025_58039_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/ad78edaaf056/41467_2025_58039_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/3bd5183816f7/41467_2025_58039_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/105b5f6b1c81/41467_2025_58039_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/2dcd86d31a6c/41467_2025_58039_Fig5_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/beaaee90db5d/41467_2025_58039_Fig6_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/4f2356ca93f5/41467_2025_58039_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/ad78edaaf056/41467_2025_58039_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/3bd5183816f7/41467_2025_58039_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/105b5f6b1c81/41467_2025_58039_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/2dcd86d31a6c/41467_2025_58039_Fig5_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05ab/11923061/beaaee90db5d/41467_2025_58039_Fig6_HTML.jpg

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