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具有高介电常数的单晶范德华层状电介质。

Single-crystalline van der Waals layered dielectric with high dielectric constant.

机构信息

Center for Nanochemistry, Beijing Science and Engineering Center for Nanocarbons, Beijing National Laboratory for Molecular Sciences, College of Chemistry and Molecular Engineering, Peking University, Beijing, China.

College of Chemistry and Chemical Engineering, Central South University, Changsha, China.

出版信息

Nat Mater. 2023 Jul;22(7):832-837. doi: 10.1038/s41563-023-01502-7. Epub 2023 Mar 9.

DOI:10.1038/s41563-023-01502-7
PMID:36894772
Abstract

The scaling of silicon-based transistors at sub-ten-nanometre technology nodes faces challenges such as interface imperfection and gate current leakage for an ultrathin silicon channel. For next-generation nanoelectronics, high-mobility two-dimensional (2D) layered semiconductors with an atomic thickness and dangling-bond-free surfaces are expected as channel materials to achieve smaller channel sizes, less interfacial scattering and more efficient gate-field penetration. However, further progress towards 2D electronics is hindered by factors such as the lack of a high dielectric constant (κ) dielectric with an atomically flat and dangling-bond-free surface. Here, we report a facile synthesis of a single-crystalline high-κ (κ of roughly 16.5) van der Waals layered dielectric BiSeO. The centimetre-scale single crystal of BiSeO can be efficiently exfoliated to an atomically flat nanosheet as large as 250 × 200 μm and as thin as monolayer. With these BiSeO nanosheets as dielectric and encapsulation layers, 2D materials such as BiOSe, MoS and graphene show improved electronic performances. For example, in 2D BiOSe, the quantum Hall effect is observed and the carrier mobility reaches 470,000 cm V s at 1.8 K. Our finding expands the realm of dielectric and opens up a new possibility for lowering the gate voltage and power consumption in 2D electronics and integrated circuits.

摘要

在亚十纳米技术节点,硅基晶体管的缩微面临着一些挑战,如超薄硅通道的界面不完美和栅极电流泄漏。对于下一代纳米电子学,具有原子厚度和悬空键自由表面的高迁移率二维(2D)层状半导体有望成为沟道材料,以实现更小的沟道尺寸、更少的界面散射和更有效的栅极场穿透。然而,由于缺乏具有原子平坦和悬空键自由表面的高介电常数(κ)介电材料等因素,2D 电子学的进一步发展受到阻碍。在这里,我们报告了一种单晶高κ(κ约为 16.5)范德华层状介电体 BiSeO 的简便合成方法。BiSeO 的厘米级单晶可以有效地剥离成原子平坦的纳米片,尺寸可达 250×200μm,厚度可达单层。利用这些 BiSeO 纳米片作为介电层和封装层,2D 材料如 BiOSe、MoS 和石墨烯表现出了改善的电子性能。例如,在二维 BiOSe 中,观察到量子霍尔效应,载流子迁移率在 1.8K 时达到 470000cmV s。我们的发现扩展了介电材料的领域,并为降低二维电子学和集成电路的栅极电压和功耗开辟了新的可能性。

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