Huang Jing-Kai, Wan Yi, Shi Junjie, Zhang Ji, Wang Zeheng, Wang Wenxuan, Yang Ni, Liu Yang, Lin Chun-Ho, Guan Xinwei, Hu Long, Yang Zi-Liang, Huang Bo-Chao, Chiu Ya-Ping, Yang Jack, Tung Vincent, Wang Danyang, Kalantar-Zadeh Kourosh, Wu Tom, Zu Xiaotao, Qiao Liang, Li Lain-Jong, Li Sean
School of Materials Science and Engineering, University of New South Wales, Sydney, New South Wales, Australia.
Department of Mechanical Engineering, The University of Hong Kong, Hong Kong, China.
Nature. 2022 May;605(7909):262-267. doi: 10.1038/s41586-022-04588-2. Epub 2022 May 11.
The scaling of silicon metal-oxide-semiconductor field-effect transistors has followed Moore's law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 10, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems.
几十年来，硅金属氧化物半导体场效应晶体管的尺寸缩放一直遵循摩尔定律，但在亚十纳米技术节点上硅的物理变薄会引入诸如漏电流等问题。二维（2D）层状半导体具有原子厚度，能实现卓越的栅极电场穿透，作为未来晶体管的沟道材料备受关注。然而，将高介电常数（κ）材料与二维材料集成，同时缩小其电容等效厚度（CET），已被证明具有挑战性。在此，我们探索可转移的超高κ单晶钙钛矿锶钛氧化物膜作为二维场效应晶体管的栅极电介质。我们的钙钛矿膜展现出理想的亚一纳米CET，且漏电流低（在2.5兆伏每厘米时小于每平方厘米10安培）。我们发现，锶钛氧化物电介质与二维半导体之间的范德华间隙减轻了因使用超高κ电介质而产生的不利边缘诱导势垒降低效应。由通过化学气相沉积法制备的可扩展二硫化钼薄膜和锶钛氧化物电介质制成的典型短沟道晶体管，其亚阈值摆幅陡峭至约每十倍频程70毫伏，开/关电流比高达10，这与最新的《器件与系统国际路线图》所建议的低功耗规格相匹配。
