Gao Tian, Deng Bin, Wang Jiang, Yi Guosheng
School of Electrical and Information Engineering, Tianjin University, Tianjin, China.
Front Neurosci. 2023 Feb 23;17:1107089. doi: 10.3389/fnins.2023.1107089. eCollection 2023.
Recurrent spiking neural network (RSNN) performs excellently in spatio-temporal learning with backpropagation through time (BPTT) algorithm. But the requirement of computation and memory in BPTT makes it hard to realize an on-chip learning system based on RSNN. In this paper, we aim to realize a high-efficient RSNN learning system on field programmable gate array (FPGA).
A presynaptic spike-driven plasticity architecture based on eligibility trace is implemented to reduce the resource consumption. The RSNN with leaky integrate-and-fire (LIF) and adaptive LIF (ALIF) models is implemented on FPGA based on presynaptic spike-driven architecture. In this architecture, the eligibility trace gated by a learning signal is used to optimize synaptic weights without unfolding the network through time. When a presynaptic spike occurs, the eligibility trace is calculated based on its latest timestamp and drives synapses to update their weights. Only the latest timestamps of presynaptic spikes are required to be stored in buffers to calculate eligibility traces.
We show the implementation of this architecture on FPGA and test it with two experiments. With the presynaptic spike-driven architecture, the resource consumptions, including look-up tables (LUTs) and registers, and dynamic power consumption of synaptic modules in the on-chip learning system are greatly reduced. The experiment results and compilation results show that the buffer size of the on-chip learning system is reduced and the RSNNs implemented on FPGA exhibit high efficiency in resources and energy while accurately solving tasks.
This study provides a solution to the problem of data congestion in the buffer of large-scale learning systems.
递归脉冲神经网络（RSNN）在基于时间反向传播（BPTT）算法的时空学习中表现出色。但BPTT对计算和内存的要求使得基于RSNN的片上学习系统难以实现。在本文中，我们旨在实现一个基于现场可编程门阵列（FPGA）的高效RSNN学习系统。
实现了一种基于资格迹的突触前脉冲驱动可塑性架构，以减少资源消耗。基于突触前脉冲驱动架构，在FPGA上实现了具有泄漏积分发放（LIF）和自适应LIF（ALIF）模型的RSNN。在该架构中，由学习信号门控的资格迹用于优化突触权重，而无需随时间展开网络。当突触前脉冲出现时，根据其最新时间戳计算资格迹，并驱动突触更新其权重。只需要将突触前脉冲的最新时间戳存储在缓冲区中以计算资格迹。
我们展示了该架构在FPGA上的实现，并通过两个实验对其进行了测试。采用突触前脉冲驱动架构，片上学习系统中突触模块的资源消耗（包括查找表（LUT）和寄存器）以及动态功耗大大降低。实验结果和编译结果表明，片上学习系统的缓冲区大小减小，在FPGA上实现的RSNN在准确解决任务的同时，在资源和能量方面表现出高效率。
本研究为大规模学习系统缓冲区中的数据拥塞问题提供了解决方案。
