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优化阴影蒸发和氧化,以实现可重现的量子约瑟夫森结电路。

Optimization of shadow evaporation and oxidation for reproducible quantum Josephson junction circuits.

机构信息

FMN Laboratory, Bauman Moscow State Technical University, Moscow, 105005, Russia.

Dukhov Automatics Research Institute (VNIIA), Moscow, 127055, Russia.

出版信息

Sci Rep. 2023 Mar 13;13(1):4174. doi: 10.1038/s41598-023-31003-1.

DOI:10.1038/s41598-023-31003-1
PMID:36914735
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC10011367/
Abstract

The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlO/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlO/Al junction fabrication with the critical current variation [Formula: see text] less than 3.9% (from 150 × 200 to 150 × 600 nm area) and 7.7% (for 100 × 100 nm area) over 20 × 20 mm chip. Finally, we fabricate separately three 5 × 10 mm chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubits on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.

摘要

超导量子比特在量子电路中最常用的物理实现是转子。有许多超导量子电路的应用,其中在芯片上重现约瑟夫森结临界电流的重现性至关重要。在这里,我们报告了一种稳健的芯片级 Al/AlO/Al 结制造方法,这是由于对阴影蒸发和氧化步骤的综合研究。我们通过实验证明了最佳约瑟夫森结电极厚度、沉积速率和沉积角度的证据,这保证了最小的电极表面和线边缘粗糙度。确定了氧化方法、压力和时间对临界电流重现性的影响。通过所提出的方法,我们展示了具有临界电流变化小于 3.9%(从 150×200 到 150×600nm 面积)和 7.7%(对于 100×100nm 面积)的 Al/AlO/Al 结制造,面积超过 20×20mm 的芯片。最后,我们分别制造了三个具有 18 个转子量子比特的 5×10mm 芯片(接近 4.3GHz 频率),在不同芯片上的量子比特之间显示出小于 1.9%的频率变化。所提出的方法和优化标准可用于稳健的晶圆级超导量子比特电路制造。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/09cffdb590af/41598_2023_31003_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/fbc63850e518/41598_2023_31003_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/b0d1068e2195/41598_2023_31003_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/09cffdb590af/41598_2023_31003_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/fbc63850e518/41598_2023_31003_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/b0d1068e2195/41598_2023_31003_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f7bc/10011367/09cffdb590af/41598_2023_31003_Fig3_HTML.jpg

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