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基于组装纳米线构建块的逻辑门与计算

Logic gates and computation from assembled nanowire building blocks.

作者信息

Huang Y, Duan X, Cui Y, Lauhon L J, Kim K H, Lieber C M

机构信息

Department of Chemistry and Chemical Biology, Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA.

出版信息

Science. 2001 Nov 9;294(5545):1313-7. doi: 10.1126/science.1066192.

Abstract

Miniaturization in electronics through improvements in established "top-down" fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades. Here we report a "bottom-up" approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.

摘要

通过改进现有的“自上而下”制造技术来实现电子器件的小型化,已接近一个临界点,在这一点上,一些基本问题预计将限制过去几十年来所见到的计算能力的急剧增长。在此,我们报告一种“自下而上”的方法,其中功能性器件元件和元件阵列是通过使用电子特性明确的半导体纳米线构建块从溶液中组装而成的。我们表明,交叉纳米线p-n结和结阵列能够以超过95%的产率进行组装,且具有可控的电学特性,此外,这些结可用于创建以纳米线作为导电沟道和栅电极的集成纳米级场效应晶体管阵列。纳米线结阵列已被配置为具有可观增益的关键或、与、或非逻辑门结构,并已用于实现基本计算。

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