University of Glasgow, School of Engineering, Rankine Building, Oakfield Avenue, Glasgow, G12 8LT, UK.
Department of Materials, University of Oxford, 16 Parks Road, Oxford, OX1 3PH, UK.
Sci Rep. 2017 Jun 7;7(1):3004. doi: 10.1038/s41598-017-03138-5.
Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 10 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance.
无结纳米线晶体管正在被研究,以解决未来 CMOS 技术中的短沟道效应。在这里,我们展示了具有金属掺杂密度的 8nm 直径硅纳米线无结晶体管,其表现出明显的 1D 电子输运特性。1D 区允许通过近乎理想的亚阈值斜率、高于 10 的导通电流与关断电流比以及室温下的高导通电流进行出色的栅极调制。作为电压和温度函数的通用电导缩放与之前关于 Luttinger 液体的报告以及低温下库仑间隙行为相似,这表明包括电子-电子相互作用在内的多体效应在描述电子输运方面很重要。这表明,为了准确模拟电子输运以优化技术,需要使用包括多体相互作用的 1D 模型来对这种纳米线器件进行建模,但也表明 1D 效应可以用于提高未来晶体管的性能。