Pendurthi Rahul, Sakib Najam U, Sadaf Muhtasim Ul Karim, Zhang Zhiyu, Sun Yongwen, Chen Chen, Jayachandran Darsith, Oberoi Aaryan, Ghosh Subir, Kumari Shalini, Stepanoff Sergei P, Somvanshi Divya, Yang Yang, Redwing Joan M, Wolfe Douglas E, Das Saptarshi
Engineering Science and Mechanics, Penn State University, University Park, PA, USA.
2D Crystal Consortium Materials Innovation Platform, Penn State University, University Park, PA, USA.
Nat Nanotechnol. 2024 Jul;19(7):970-977. doi: 10.1038/s41565-024-01705-2. Epub 2024 Jul 23.
The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.
半导体行业正在向“超越摩尔定律”时代过渡，这一转变是由采用三维（3D）集成方案驱动的，该方案突破了传统二维缩放的限制。尽管创新的封装解决方案已使3D集成电路（IC）在商业上可行，但硅通孔和微凸点的引入增加了面积开销，并引入了寄生电容，限制了整体性能。单片3D集成（M3D）被视为3D IC的未来，但由于上层的热处理预算有限，其在硅IC中的应用面临障碍，这可能会降低器件性能。为克服这些限制，碳纳米管和二维半导体等新兴材料已被集成到硅IC的后端。在此，我们报告互补WSe场效应晶体管的M3D集成，其中n型场效应晶体管位于第1层，p型场效应晶体管位于第2层。特别是，我们通过间距小于1μm的300nm通孔实现了密集且可缩放的集成，连接了第1层和第2层中的300多个器件。此外，我们还有效地实现了垂直集成逻辑门，包括反相器、与非门和或非门。我们的演示突出了二维材料在推进互补金属氧化物半导体电路中的M3D集成方面的作用。
