School of Electrical Engineering, Graphene/2D Materials Research Center , KAIST , Daehak-ro , Daejeon 34141 , Republic of Korea.
System LSI, Samsung Electronics , Samsung-ro , Giheung-gu, Yongin-Si , Gyeonggi-do 17113 , Republic of Korea.
ACS Appl Mater Interfaces. 2018 Nov 21;10(46):40212-40218. doi: 10.1021/acsami.8b11396. Epub 2018 Nov 6.
We present a tunneling field-effect transistor based on a vertical heterostructure of highly p-doped silicon and n-type MoS. The resulting p-n heterojunction shows a staggered band alignment in which the quantum mechanical band-to-band tunneling probability is enhanced. The device functions in both tunneling transistor and conventional transistor modes, depending on whether the p-n junction is forward or reverse biased, and exhibits a minimum subthreshold swing of 15 mV/dec, an average of 77 mV/dec for four decades of the drain current, a high on/off current ratio of approximately 10 at a drain voltage of 1 V, and fully suppressed ambipolar behavior. Furthermore, low-temperature electrical measurements demonstrated that both trap-assisted and band-to-band tunneling contribute to the drain current. The presence of traps was attributed to defects within the interfacial oxide between silicon and MoS.
我们提出了一种基于高掺杂硅和 n 型 MoS 垂直异质结构的隧穿场效应晶体管。所得的 p-n 异质结表现出交错能带排列,其中量子力学能带对带隧穿概率增强。该器件在隧穿晶体管和传统晶体管模式下都能工作,具体取决于 p-n 结是正向偏置还是反向偏置,并表现出 15 mV/dec 的最小亚阈值摆幅,对于四个电流的十位数,平均为 77 mV/dec,在 1 V 的漏电压下,高导通/关断电流比约为 1,并且完全抑制了双极性行为。此外,低温电学测量表明,陷阱辅助隧穿和能带对带隧穿都有助于漏电流。陷阱的存在归因于硅和 MoS 之间界面氧化物中的缺陷。