Lee Yongsu, Kim Sunmean, Lee Ho-In, Kim Seung-Mo, Kim So-Young, Kim Kiyung, Kwon Heejin, Lee Hae-Won, Hwang Hyeon Jun, Kang Seokhyeong, Lee Byoung Hun
Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea.
ACS Nano. 2022 Jul 26;16(7):10994-11003. doi: 10.1021/acsnano.2c03523. Epub 2022 Jun 28.
Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼10) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-:2',3'-]thieno[3,2-]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power-delay product performance (∼122 aJ) with extremely low power (∼0.15 μW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.
在窄偏置区域的反双极开关（AAS）器件对于解决三值逻辑电路的固有漏电流问题是必要的。在本研究中，使用ZnO和二萘并[2,3-b:2',3'-d]噻吩并[3,2-b]噻吩异质结结构成功展示了具有非常高的峰谷比（约10）和可调工作范围特性的AAS器件。整个器件集成在低于200°C的低热预算下完成，这使得该AAS器件与单片3D集成兼容。采用该AAS器件设计的1三进制三值全加器表现出优异的功率延迟积性能（约122 aJ），具有极低的功耗（约0.15μW，比参考电路低7倍），并且器件数量比其他三值器件候选方案更少。
