Arutchelvan Goutham, Smets Quentin, Verreck Devin, Ahmed Zubair, Gaur Abhinav, Sutar Surajit, Jussot Julien, Groven Benjamin, Heyns Marc, Lin Dennis, Asselberghs Inge, Radu Iuliana
IMEC, Leuven, Belgium.
KU Leuven, Leuven, Belgium.
Sci Rep. 2021 Mar 23;11(1):6610. doi: 10.1038/s41598-021-85968-y.
Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.
二维半导体材料被认为是实现终极器件尺寸缩小的理想候选材料。然而，目前仍缺乏对不同器件尺寸缩小对性能和可变性影响的系统性研究。在此，我们研究了在大面积生长的MoS材料上制造的1300个器件的缩小行为，这些器件的沟道长度低至30nm，接触长度低至13nm，电容有效氧化物厚度（CET）低至1.9nm。这些器件展现出一流的性能，跨导为185μS/μm，最小亚阈值摆幅（SS）为86mV/dec。我们发现，缩小顶部接触长度对三层MoS晶体管的接触电阻和静电学没有影响，因为边缘注入占主导。此外，我们确定在短沟道长度下会发生SS退化，并且可以通过减小CET和降低肖特基势垒高度来减轻。最后，通过功率性能面积（PPA）分析，我们提出了材料改进路线图，以使二维器件与硅全栅器件具有竞争力。
