Jiang Jianfeng, Xu Lin, Qiu Chenguang, Peng Lian-Mao
Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing, China.
Nature. 2023 Apr;616(7957):470-475. doi: 10.1038/s41586-023-05819-w. Epub 2023 Mar 22.
The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal-oxide-semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. ). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.
国际器件与系统路线图(IRDS)预测,对于基于硅的金属氧化物半导体(MOS)场效应晶体管(FET),栅极长度的缩放将在12纳米处停止,最终电源电压不会降至低于0.6伏(参考文献)。这定义了基于硅的芯片缩放过程结束时的最终集成密度和功耗。近年来,具有原子级厚度的二维(2D)层状半导体已被探索作为支持进一步小型化和集成电子的潜在沟道材料。然而,到目前为止,没有基于2D半导体的FET表现出能够超越最先进的硅FET的性能。在此,我们报告一种以具有高热速度的二维硒化铟(InSe)为沟道材料的FET,其在0.5伏电压下工作,实现了创纪录的6毫西门子/微米的高跨导以及饱和区83%的室温弹道比,超过了任何已报道的硅FET。开发了一种钇掺杂诱导的相变方法来与InSe形成欧姆接触,并且InSe FET的沟道长度缩小至10纳米。我们的InSe FET能够以每十倍频程75毫伏的低亚阈值摆幅(SS)和22毫伏/伏的漏极诱导势垒降低(DIBL)有效地抑制短沟道效应。此外,在10纳米弹道InSe FET中可靠地提取出62欧姆·微米的低接触电阻,导致其固有延迟更小,能量延迟积(EDP)远低于预测的硅极限。