Kong Lingan, Zhang Xiaodong, Tao Quanyang, Zhang Mingliang, Dang Weiqi, Li Zhiwei, Feng Liping, Liao Lei, Duan Xiangfeng, Liu Yuan
Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics, Hunan University, 410082, Changsha, China.
State Key Lab of Solidification Processing, College of Materials Science and Engineering, Northwestern Polytechnical University, 710072, Xi'an, China.
Nat Commun. 2020 Apr 20;11(1):1866. doi: 10.1038/s41467-020-15776-x.
Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. However, the polarity control of 2D transistors and the achievement of complementary logic functions remain critical challenges. Here, we report a doping-free strategy to modulate the polarity of WSe transistors using same contact metal but different integration methods. By applying low-energy van der Waals integration of Au electrodes, we observed robust and optimized p-type transistor behavior, which is in great contrast to the transistors fabricated on the same WSe flake using conventional deposited Au contacts with pronounced n-type characteristics. With the ability to switch majority carrier type and to achieve optimized contact for both electrons and holes, a doping-free logic inverter is demonstrated with higher voltage gain of 340, at the bias voltage of 5.5 V. Furthermore, the simple polarity control strategy is extended for realizing more complex logic functions such as NAND and NOR.
二维(2D)半导体在超薄体晶体管的发展中引起了广泛关注。然而,二维晶体管的极性控制以及互补逻辑功能的实现仍然是关键挑战。在此,我们报告一种无掺杂策略,该策略使用相同的接触金属但不同的集成方法来调制WSe晶体管的极性。通过应用金电极的低能范德华集成,我们观察到了稳健且优化的p型晶体管行为,这与使用具有明显n型特性的传统沉积金接触在同一WSe薄片上制造的晶体管形成了鲜明对比。凭借能够切换多数载流子类型并实现电子和空穴的优化接触的能力,在5.5 V的偏置电压下展示了具有340更高电压增益的无掺杂逻辑反相器。此外,这种简单的极性控制策略被扩展用于实现更复杂的逻辑功能,如与非门和或非门。